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Intel Arria V SoC FPGA开发应用方案

发表时间:2019-12-25 13:14

Intel公司的Arria® V SoC FPGA和Arria® 10 SoC FPGA基于TSMC 20 nm工艺,是行业性能最高的 28 nm SoC FPGA.采用同样的双核ARM Cortex-A9处理器.因此,当完成Arria® V SoC FPGA设计,可以通过软件升级到Arria® 10 SoC FPGA设计.FPGA器件具有双核ARM Cortex-A9 MPCore处理器和ARM CoreSight*调试和跟踪技术,I3速度级的CPU时钟速率为1.05GHz,C4速度级的CPU时钟速率为925MHz,C5和I5速度级的CPU时钟速率为800MHz,而C6速度级的CPU时钟速率为700MHz.协处理器为带有矢量浮点(VFP) v3双精度浮点单元的ARM NEON*媒体处理引擎,用于每个处理器,窥探控制单元(SCU)和加速相干端口(ACP).主要用在远程无线单元和移动骨干网在内的无线基础设施设备,固网10G/40G 线路卡,桥接和聚合以及GPON,广播演播室和分配设备包括专业 A/V 和视频会议,军用导航,控制和智能设备,以及测试和测量设备,医疗成像设备与多功能打印机.


本文介绍了Arria® V SoC FPGA主要特性和硬处理器系统概述,以及Arria® V SoC FPGA开发板主要特性,开发板框图,电路图,材料清单和PCB设计图.

The Arria® V SoC FPGA and Arria® 10 SoC FPGA utilize the same dual-core ARM Cortex-A9 processor. Therefore, when your Arria® V SoC FPGA design is ready for a performance upgrade you can easily migrate your software to the Arria® 10 SoC FPGA. Based on the TSMC 20 nm process, the Arria® 10 SoC FPGA offers for a performance upgrade path for Arria® V SoC FPGA designs with easy software migration.

Arria® V SoC FPGA主要特性:

图1.Arria® V SoC FPGA硬处理器系统概述

Arria® V SoC FPGA主要特性:


Device

All Arria® V SoC FPGA Devices (SX, ST)

Processor

Dual-core ARM Cortex-A9 MPCore processor with ARM CoreSight* debug and trace technology
1.05 GHz CPU clock rate in -I3 speed grade
925 MHz CPU clock rate in -C4 speed grade
800 MHz CPU clock rate in -C5, -I5 speed grades
700 MHz CPU clock rate in -C6 speed grade

Coprocessors

ARM NEON* media processing engine with Vector Floating-Point (VFP) v3 double-precision floating point unit for each processor, Snoop Control Unit (SCU), Acceleration Coherency Port (ACP)

Level 1 cache

32 KB L1 instruction cache, 32 KB L1 data cache

Level 2 cache

512 KB shared L2 cache

On-chip memory

64 KB on-chip RAM, 64 KB on-chip ROM

HPS hard memory controller

Multiport SDRAM controller with support for DDR2, DDR3, DDR3L, and LPDDR2 with optional error correction code (ECC) support
533 MHz/1066 Mbps external memory interface
User-configurable memory width of 8, 16, 16+ECC, 32, 32+EEC
Up to 4 GB address range, with built-in memory protection control

Quad serial peripheral interface (SPI) flash controller

Supports SPIx1, SPIx2, or SPIx4 (quad SPI) serial NOR flash devices
Up to four chip selects

SD/SDIO/MMC controller

Supports SD, eSD, SDIO, eSDIO, MMC, eMMC, and CE-ATA with integrated DMA

NAND flash controller

Supports 8 bit ONFI 1.0 NAND flash devices
Programmable hardware ECC for Single-Level Cell (SLC) and Multi-Level Cell (MLC) devices

Ethernet media access controller (EMAC)

2 x 10/100/1000 EMAC with RGMII external PHY interface and integrated DMA

USB On-The-Go controller (OTG)

2 x USB 2.0 OTG controllers with ULPI external PHY interface and integrated DMA

UART controller

2 x UART 16550 compatible

SPI controller

2 x SPI masters
2 x SPI slaves

I2C controller

4 x I2C

General-purpose I/O (GPIO)

Up to 71 GPIO and 14 input-only pins, with digital de-bounce and configurable interrupt mode

Direct memory access (DMA) controller

8-channel direct memory access (DMA)
Supports flow control with 31 peripheral handshake interfaces

Timers

Private interval and watchdog timer for each processor
Global timer for processor subsystem
4X general-purpose timers
2X watchdog timers

Maximum HPS I/O

208

HPS phased-locked loops (PLLs)

3


Arria® V SoC FPGA开发板

The Altera® Arria® V system on a chip (SoC) Development Kit is a complete design
environment that includes both the hardware and software you need to developArria V SoC designs.

Arria® V SoC FPGA开发板主要特性:

■ One Arria V SoC (5ASTFD5K3F40I3) in a 896-pin FBGA package
■ FPGA configuration circuitry
■ Active Serial (AS) x1 or x4 configuration (EPCQ256SI16N)
■ MAX® V CPLD (5M2210ZF256) in a 256-pin FBGA package as the SystemController
■ Flash fast passive parallel (FPP) configuration
■ MAX II CPLD (EPM570GF100) as part of the on-board USB-BlasterTM II for usewith the Quartus® II Programmer
■ Clocking circuitry
■ Si570, Si571, and Si5338 programmable oscillators
■ 50-MHz, 66-MHz, 100-MHz, 125-MHz programmable oscillators
■ SMA input (LVCMOS)
■ Memory
■ One 1,024-Mbyte (MB) HPS DDR3 SDRAM with error correction code (ECC)support
■ Two 1,024-MB FPGA DDR3 SDRAM
■ One 512-Megabit (Mb) quad serial peripheral interface (QSPI) flash
■ One 512-Mb CFI synchronous flash
■ One 256-Mb NOR flash (EPCQ device)
■ One 32-Kilobit (Kb) I2C serial electrically erasable PROM (EEPROM)
■ One Micro SD flash memory card
■ Communication Ports
■ One PCI Express x4 Gen1 socket
■ Two FPGA mezzanine card (FMC) ports
■ One USB 2.0 on-the-go (OTG) port
■ One Gigabit Ethernet port
■ Two 10/100 Ethernet ports
■ Two SFP+ ports
■ Two RS-232 UART (through the mini-USB port)
■ One real-time clock
■ General user input/output
■ LEDs and displays
■ Eight user LEDs
■ One configuration load LED
■ One configuration done LED
■ One error LED
■ Three configuration select LEDs
■ Four on-board USB-Blaster II status LEDs
■ Two FMC interface LEDs
■ Two UART data transmit and receive LEDs
■ One power on LED
■ One two-line character LCD display
■ Push buttons
■ One CPU reset push button
■ One MAX V reset push button
■ One program select push button
■ One program configuration push button
■ Eight general user push buttons
■ DIP switches
■ One JTAG chain control DIP switch
■ One board settings DIP switch
■ One FPGA configuration mode DIP switch
■ One general user DIP switch
■ Power supply
■ 14–20-V (laptop) DC input
■ Mechanical
■ 7.175" × 9" rectangular form factor

图2.Arria® V SoC FPGA开发板框图
 图3.Arria® V SoC FPGA开发板外形图

图4.Arria® V SoC FPGA开发板电路图(1)

图5.Arria® V SoC FPGA开发板电路图(2)

图6.Arria® V SoC FPGA开发板电路图(3)

图7.Arria® V SoC FPGA开发板电路图(4)

图8.Arria® V SoC FPGA开发板电路图(5)

图9.Arria® V SoC FPGA开发板电路图(6)

图10.Arria® V SoC FPGA开发板电路图(7)

图11.Arria® V SoC FPGA开发板电路图(8)

图12.Arria® V SoC FPGA开发板电路图(9)

图13.Arria® V SoC FPGA开发板电路图(10)

图14.Arria® V SoC FPGA开发板电路图(11)

图15.Arria® V SoC FPGA开发板电路图(12)

图16.Arria® V SoC FPGA开发板电路图(13)

图17.Arria® V SoC FPGA开发板电路图(14)

图18.Arria® V SoC FPGA开发板电路图(15)

图19.Arria® V SoC FPGA开发板电路图(16)

图20.Arria® V SoC FPGA开发板电路图(17)

图21.Arria® V SoC FPGA开发板电路图(18)

图22.Arria® V SoC FPGA开发板电路图(19)

图23.Arria® V SoC FPGA开发板电路图(20)

图24.Arria® V SoC FPGA开发板电路图(21)

图25.Arria® V SoC FPGA开发板电路图(22)

图26.Arria® V SoC FPGA开发板电路图(23)

图27.Arria® V SoC FPGA开发板电路图(24)

图28.Arria® V SoC FPGA开发板电路图(25)

图29.Arria® V SoC FPGA开发板电路图(26)

图30.Arria® V SoC FPGA开发板电路图(27)

图31.Arria® V SoC FPGA开发板电路图(28)

图32.Arria® V SoC FPGA开发板电路图(29)

图33.Arria® V SoC FPGA开发板电路图(30)

图34.Arria® V SoC FPGA开发板电路图(31)

图35.Arria® V SoC FPGA开发板电路图(32)

图36.Arria® V SoC FPGA开发板电路图(33)

图37.Arria® V SoC FPGA开发板电路图(34)

图38.Arria® V SoC FPGA开发板电路图(35)

图39.Arria® V SoC FPGA开发板电路图(36)

图40.Arria® V SoC FPGA开发板电路图(37)

图40.Arria® V SoC FPGA开发板电路图(37)

图41.Arria® V SoC FPGA开发板电路图(38)

图42.Arria® V SoC FPGA开发板电路图(39)

图43.Arria® V SoC FPGA开发板电路图(40)

图44.Arria® V SoC FPGA开发板电路图(41)

图45.Arria® V SoC FPGA开发板电路图(42)


图46.Arria® V SoC FPGA开发板PCB设计图(1)

图47.Arria® V SoC FPGA开发板PCB设计图(2)


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